Generally, there are two basic types of ADC converters: a) synchronous and b) asynchronous. Synchronous ADCs are sampled at fixed intervals, as in FIG. 1A; and asynchronous ADCs, such as FIG. 1B, are sampled at variable intervals. Both types of ADCs have their weaknesses.
With synchronous ADCs, such as in FIG. 1A, there is the problem with its “quantization error” regarding measuring of analog input signals. Eg. if an input signal is between levels to be sampled by the ADC, when a sampling is “forced” by a clock, the digital sample, which coincides to one the ADC levels surrounding the signal, is generated. At this instant, a small error (voltage quantization error) is introduced in to the system, and a small fraction of the signal information is “lost”.
Moreover, regarding synchronous ADCs, whether the input is full scale or half-full scale or one-tenth full-scale, the amount of quantization noise is actually the same; therefore, as the signal becomes smaller, the ratio of signal energy to quantization noise energy actually gets proportionately smaller.
One way of expressing a signal to noise ratio, is that of “Effective Number of Bits” or “ENOB”. ENOB expresses the signal to noise ratio in terms of bits. As the input amplitude goes down, and the noise amplitude does not go down, then the ENOB also goes down—in other words, the precision of the digital output drops as the analog input signal amplitude drops since the noise amplitude holds steady.
In a synchronous ADC, if the signal level decreases, the noise [quantization error] remains the same, so there is a loss of signal to noise ratio. If quantization noise is the only noise source, specifically signal to quantization noise ratio (SQNR) decreases. In reality, the noise has multiple components such as thermal noise, quantization noise, noise due to non-linearity linearity of devices, etc. Even in this case with all noise sources, SNR decreases as signal amplitude goes down or any of the noise sources increase.
There is an alternative approach to analog to digital conversion, using what is known as an “asynchronous analog to digital converter” (“asynchronous ADC”), such as in FIG. 1B. With asynchronous converters, such as discussed in “A non-uniform sampling technique for A/D conversion, Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on, vol., no., pp. 1220-1223 vol. 2, 3-6 May 1993”, by Sayiner, N.; Sorensen, H. V.; Viswanathan, T. R. (“Sayiner”); a digital sample is generated when the input analog signal crosses a threshold (“level”). This is advantageous, because there is no voltage quantization error when signal crosses a known “level”. This means that there is no voltage quantization noise in the output samples from an asynchronous ADC by itself. Please see FIGS. 1A-2B regarding the quantization noise, as shall be explained, below.
Moreover, the output of the asynchronous ADC is not directly usable by synchronous signal processing circuits that follow the ADC. Therefore, at the time of the conversion, a “2-tuple” is generated upon crossing a threshold, that of an output level and a “timestamp”, which may be used in further processing to create synchronous samples usable by standard synchronous signal processing circuits.
However, the timestamp itself has quantization noise, a “time” quantization noise. This time quantization step and the associated effects are illustrated in FIG. 2A. Let us assume that the signal crosses level V2, at time “T”. Now, ideally [V2, T] would be the asynchronous output. To reduce complexity the time “T” is stored in quantized form—chosen from the edges of a high resolution clock (T1, T2, T3 . . . ). So, instead of [V2, T], [V2, T2] is the 2-tuple actually stored, and hence a time quantization error ΔT=|T2−T| is introduced.
As these time grids are assumed to be finely spaced from each other, the signal in this region can be approximated by a straight line with slope dV/dT. Hence the voltage quantization error, ΔV, introduced due to this time quantization error can be approximated as ΔV=dV/dT·ΔT. This shows that this kind of quantization error is proportional to signal, and hence the Signal to quantization noise from such quantization noise sources hold constant even if signal energy drops. In systems where this noise source is dominant, the SNR (or equivalently ENOB) does not drop with decrease in signal level.
Now, a given system may have different noise sources—elastic noise sources (like SNQR due to time quantization, jitter noise, etc.) which scale with signal levels, and inelastic noise sources (like voltage quantization noise present in synchronous ADCs, thermal noise, flicker noise, etc.) which do not scale with signals. If the dominant noise source is elastic in nature, the SNR (or ENOB) does not fall even if signal amplitude falls. Asynchronous systems can be designed such that inelastic noise sources become dominant only beyond a point—and till then the SNR does not fall even if signal falls. This region where the SNRs hold steady, is called a “flat band”—after which the inelastic noise sources become dominant, and the ENOB starts falling (similar to synchronous ADCs) as signal levels fall.
Moreover, regarding SQNR, as is understood by the present inventors, SQNR is proportional to the value computed by the expression, “−log (bandwidth*time quantization error)”. As the bandwidth of the asynchronous ADC goes down, and the SQNR improves, for a given time quantization error.
FIG. 2B illustrates a “flat band” for an asynchronous ADC converter. As is illustrated, a hypothetical customer requirement is proposed. When the customer seeks 11.5 effective bits at ¼ fullscale, a conventional ADC provides that using a 14 bit (13.5 effective bits) ADC whereas the asynchronous ADC (with a 2-bit flat band) can provide the same with 12 effective bits ADC. Typically lower bit requirements translate to exponentially lower power requirements.
The red line shows the decrease in ENOB for a 12 effective bits synchronous ADC, which provides only 10 effective bits at ¼ full scale, thereby not satisfying the customers' requirements. Furthermore, traditional asynchronous ADC architectures, however, each have their own drawbacks.
As alluded to above, for conventional asynchronous ADC, the sampling rate is a function of the signal amplitude, number of active levels used for level crossing detection and signal frequency. Moreover, for some signal types, classical asynchronous ADC, as reported in Sayiner's work, tend to oversample the signal. For e.g., for an 8 level asynchronous ADC, a full-scale sine wave is sampled sixteen times, which is 8-times the minimum samples (“Nyquist rate”) required for signal reconstruction. A 16 level asynchronous ADC may sample the same signal thirty two times, which is sixteen times more than the minimum required. Therefore, in the prior art, one always have an extremely large amount of oversampling.
That in turn translates to large amounts of power wasted especially if most of the samples are thrown away by the signal processing chain following the ADC. In addition, another drawback of traditional asynchronous ADCs is that they produce asynchronous (non-uniformly spaced in time) samples. Since the domain of asynchronous signal processing is nascent, most applications prefer to process synchronous samples. However, converting these non-uniform samples into uniform samples is a complex and power hungry task.
Furthermore, when converting, it would be advantageous to have an asynchronous ADC that addresses at least some of these drawbacks.